-
-
-
[
MultiPlatform]
two_d_dct_serial.zip
ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be used to transform learning polynomial algorithm DCT
-
[
Others]
risc_cpu.rar
This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which
came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the ...
-
-
-
[
Others]
usbhostslave.zip
USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements
-
[
Visual C++ (VC++)]
cccp.rar.zip
... /soft/3894.htm- 12k-web snapshot-like web-to Verilog description DES encryption algorithm (e-books) [traditional] ... the ... algorithm for example, to see how to use Verilog expression ... ... Re : Verilog description DES encryption algorithm (e-books) from ...
-
-
-
[
MultiPlatform]
VerilogHDL.rar
Verilog HDL procedures, the development of hardware are interested or needs a friend to see down quickly down