verilog code resource search result, page 76, Verysource

[Windows_Unix] adder16bit.rar 16 high-speed adder using Verilog language has been successful simulation can be run
Category: VHDL-FPGA-Verilog Upload User：veryhu Size：2K
[MultiPlatform] Viterbidecoder.rar Viterbi decoder low power design Verilog coding complete procedures can be used directly
Category: VHDL-FPGA-Verilog Upload User：yutian0522 Size：377K
[Others] Arbiter.rar Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Category: VHDL-FPGA-Verilog Upload User：fsgsgth Size：2K
[Others] Comparators_16B.rar Verilog achieve optimization of 16 compared with the output can be greater than, less than, equal to. Modular design, which can be expanded to 32
Category: VHDL-FPGA-Verilog Upload User：kepu828 Size：21K
[Visual C++ (VC++)] avr_core2_VHDL.zip avr core verilog for asic design
Category: VHDL-FPGA-Verilog Upload User：zhaobf Size：82K
[MultiPlatform] xljcq.rar sequence generator on the Verilog. Hope you can help.
Category: VHDL-FPGA-Verilog Upload User：bestvpn Size：3K
[MultiPlatform] hamin0132.rar series guitar code modules, using Verilog languages, as Modelsim of a project.
Category: VHDL-FPGA-Verilog Upload User：hmj08123 Size：31K
[MultiPlatform] crc3321.rar Cyclic Check Code VERILOG source, the MODELSIM of a project.
Category: VHDL-FPGA-Verilog Upload User：zhanglijun Size：27K
[MultiPlatform] parity2258.rar parity VERILOG source code for MODELSIM of a project. A test document.
Category: VHDL-FPGA-Verilog Upload User：boshan01 Size：25K
[Unix_Linux] verilog_code_673.rar basic unit of Verilog modules. Helpful for beginners.
Category: VHDL-FPGA-Verilog Upload User：kantill Size：100K

keyword: verilog