verilog code resource search result, page 82, Verysource

[Windows_Unix] simple_fifo.rar verilog HDL original code a simple synchronous FIFO original code, which can be integrated
Category: VHDL-FPGA-Verilog Upload User：lplp2008 Size：1K
[Others] verilog_ppt.rar Huawei internal verilog materials ppt version. More detailed.
Category: VHDL-FPGA-Verilog Upload User：yhmled Size：257K
[Others] 16bit_booth_multiplier_STG.rar verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Category: VHDL-FPGA-Verilog Upload User：zhufy121 Size：2K
[Others] dirital_clock_7.rar verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
Category: VHDL-FPGA-Verilog Upload User：dzqled Size：1K
[Others] dff_UDP.rar verilog achieve, UDP asynchronous reset with a description of the fringe is triggered D flip-flop, test test pass
Category: VHDL-FPGA-Verilog Upload User：ruyijiqi Size：1K
[Others] fifo_datapath.rar verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
Category: VHDL-FPGA-Verilog Upload User：hfwhc118 Size：2K
[Others] I2C_verilog.rar I2C Bus verilog achieving source, I2C bus integrity of the basic functions
Category: VHDL-FPGA-Verilog Upload User：xhpypqy Size：20K
[Others] I2C_Controller.zip TW9910 initialization procedures. Verilog.
Category: VHDL-FPGA-Verilog Upload User：mmwzb2008 Size：3K
[VFP] risc_spm.rar advanced digital design with the verilog h dl
Category: VHDL-FPGA-Verilog Upload User：wfhgdz Size：4K
[Others] PUKverilogPPT1-9PAGE.rar collection of the Beijing University verilog the PPT, a member of the useful, which is 1-9 chapter Subsequently the remaining Upload
Category: VHDL-FPGA-Verilog Upload User：lgd0928 Size：614K

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