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keyword: verilog

  • [Visual C++ (VC++)] fen.rar Verilog, 4,5 dividers, five dividers ratio of 3:2
    Category: VHDL-FPGA-Verilog Upload User：wgj_gy Size：150K
  • [C/C++] pn_code.rar coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures
    Category: VHDL-FPGA-Verilog Upload User：jate999 Size：36K
  • [C/C++] datastructuredescribingExercisesSetanswer.Z a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the ...
    Category: VHDL-FPGA-Verilog Upload User：h88291926 Size：110K
  • [Matlab] adder.rar The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
    Category: VHDL-FPGA-Verilog Upload User：stv166 Size：131K
  • [Windows_Unix] sap1.rar using Verilog This is a simple written by the processor, although with only five directives, through this example, to understand cpu architecture, how to develop processor, it would be very enlightening.
    Category: VHDL-FPGA-Verilog Upload User：tjbfgc Size：33K
  • [DOS] xsoc-beta-093.zip This free cpu-ip! use verilog
    Category: VHDL-FPGA-Verilog Upload User：new0619 Size：3263K
  • [Others] code of 8051verilog Verilog OF 8051
    Category: VHDL-FPGA-Verilog Upload User：gujunhao Size：2139K
  • [MultiPlatform] cordic.rar The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.
    Category: VHDL-FPGA-Verilog Upload User：tyin123 Size：4K
  • [MultiPlatform] arbit.rar Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
    Category: VHDL-FPGA-Verilog Upload User：rainco Size：6K
  • [MultiPlatform] backward.rar Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
    Category: VHDL-FPGA-Verilog Upload User：slhang369 Size：3K