verilog code resource search result, page 40, Verysource

[Others] CHICAGO5Manual.rar ... technical personnel and college students, so that you can in the shortest possible period of time to master the application of FPGA and VHDL/AHDL/Verilog HDL logic design of the electronic weapon, quickly adding advanced electronic design talent ranks.
Category: VHDL-FPGA-Verilog Upload User：jina1977 Size：252K
[Others] CPU.rar CPU of verilog implementation
Category: VHDL-FPGA-Verilog Upload User：xjg_hxy Size：71K
[VHDL] sdram-control-verilog.rar This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.
Category: VHDL-FPGA-Verilog Upload User：lihui11804 Size：968K
[VHDL] FIFO_Asyn.rar Source code for asyn_fifo using verilog language.
Category: VHDL-FPGA-Verilog Upload User：jchk_cpa Size：149K
[VHDL] ddr-sdram.rar Verilog source code for DDR SDRAM controler design,including guide book in chinese.
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[VHDL] coeff_rom_0_7.rar FIR filter basic verilog code for implementation
Category: VHDL-FPGA-Verilog Upload User：bjztst Size：2K
[VHDL] coeff_rom_1_6.rar FIR filter basic verilog code for implementation
Category: VHDL-FPGA-Verilog Upload User：dsmobil Size：2K
[VHDL] coeff_rom_2_5.rar FIR filter basic verilog code for implementation
Category: VHDL-FPGA-Verilog Upload User：jygdz002 Size：2K
[VHDL] coeff_rom_3_4.rar FIR filter basic verilog code for implementation
Category: VHDL-FPGA-Verilog Upload User：qdjykj Size：2K
[VHDL] adder.rar FIR filter basic verilog code for implementation
Category: VHDL-FPGA-Verilog Upload User：zhw40304 Size：1K

keyword: verilog