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[
Others]
maxbijiao.rar
Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory
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VHDL]
add_tree.v.bak.rar
FPGA-based gate-level logic implementation of rapid multiplication of the verilog source.
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MultiPlatform]
crc.rar
Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared using verilog HDL
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[
VHDL]
SAP-1.rar
SAP-1 hardware description language (using the Verilog language)
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[
VHDL]
jiaotongdeng.rar
This procedure is the use of state machine to control the traffic lights verilog code
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