verilog code resource search result, page 39, Verysource

[Others] FIFO.rar Asynchronous FIFO controller Verilog Design and Implementation
Category: VHDL-FPGA-Verilog Upload User：greenled06 Size：6K
[Others] I2CSlave.rar achieve the Verilog HDL simulation I2C Slave
Category: VHDL-FPGA-Verilog Upload User：tzy6361 Size：1K
[Others] 8251Verilog.rar Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
Category: VHDL-FPGA-Verilog Upload User：shfe5518 Size：16K
[Others] Verilog.rar
Category: VHDL-FPGA-Verilog Upload User：gzdiguang Size：1684K
[Others] des.rar Using Verilog language code of the Data Encryption Standard, in the simulation had QUARTUS5.1
Category: VHDL-FPGA-Verilog Upload User：osram_2007 Size：1403K
[Others] FIFO-DC.rar FIFO procedures have been in the Verilog in ModelSim compiler and can be passed through the integrated DC
Category: VHDL-FPGA-Verilog Upload User：byc5566 Size：60K
[VHDL] spitoi2s3.rar spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
Category: VHDL-FPGA-Verilog Upload User：huanuo_001 Size：5K
[VHDL] rng.rar random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
Category: VHDL-FPGA-Verilog Upload User：wishlxc Size：92K
[VHDL] veriloghdlcsdm.rar Verilog hdl using hardware description language to write an example of the procedure, led, and highly scalable, welcome to download.
Category: VHDL-FPGA-Verilog Upload User：gzsgzh Size：1K
[VHDL] FPGA.rar VHDL、Verilog HDL
Category: VHDL-FPGA-Verilog Upload User：shenzblk Size：1998K

keyword: verilog