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[
VHDL]
lai_PWM.rar
FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in
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[
VHDL]
svc_timer33ms.rar
Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
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[
VHDL]
Segment2.rar
the realization of paragraph ep2c5 register verilog language, quartus 2 Simulation
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[
VHDL]
Segment1.rar
Register ep2c5 achieve above experiment a verilog language, quartus 2 Simulation
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[
VHDL]
BaseGate.rar
ep2c5 the realization of logic gates verilog language, quartus 2 Simulation
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[
VHDL]
Timer.rar
verilog language to achieve ep2c5 timer, quartus 2 Simulation
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[
Others]
OddFP.rar
verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency
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[
Others]
CPI.rar
verilog easy to achieve CPI general-purpose interface
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[
Others]
InvMod_test.rar
verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel