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  • [VHDL] lai_PWM.rar FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in
    Category: VHDL-FPGA-Verilog Upload User:yzg_tc Size:847K
  • [VHDL] svc_timer33ms.rar Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
    Category: VHDL-FPGA-Verilog Upload User:kyyxmm Size:746K
  • [VHDL] Segment2.rar the realization of paragraph ep2c5 register verilog language, quartus 2 Simulation
    Category: VHDL-FPGA-Verilog Upload User:ljxandwhm Size:367K
  • [VHDL] Segment1.rar Register ep2c5 achieve above experiment a verilog language, quartus 2 Simulation
    Category: VHDL-FPGA-Verilog Upload User:whfeng1976 Size:396K
  • [VHDL] BaseGate.rar ep2c5 the realization of logic gates verilog language, quartus 2 Simulation
    Category: VHDL-FPGA-Verilog Upload User:qhdfrp Size:313K
  • [VHDL] Timer.rar verilog language to achieve ep2c5 timer, quartus 2 Simulation
    Category: VHDL-FPGA-Verilog Upload User:sumiron Size:486K
  • [Others] OddFP.rar verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency
    Category: VHDL-FPGA-Verilog Upload User:tang239385 Size:1K
  • [Others] paobiao.rar verilog digital stopwatch to achieve accurate to 10ms
    Category: VHDL-FPGA-Verilog Upload User:huang633 Size:2K
  • [Others] CPI.rar verilog easy to achieve CPI general-purpose interface
    Category: VHDL-FPGA-Verilog Upload User:cltqzc Size:3K
  • [Others] InvMod_test.rar verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel
    Category: VHDL-FPGA-Verilog Upload User:gdszzhy Size:5K