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keyword: verilog

  • [Others] Verilogdianzirili.rar Verilog-based electronic calendar and e-clock procedures, can be adjusted date, week, time of minutes and hours, through several models to display a calendar and time.
    Category: VHDL-FPGA-Verilog Upload User：houp9834 Size：3K
  • [Others] Verilogshumaguan.rar Verilog-based digital control analog scanning procedures, two types of display, a digital control-by-show, and the other is with all digital tube display.
    Category: VHDL-FPGA-Verilog Upload User：wwwjnhzjc Size：2K
  • [Others] FIFO_Syn.rar Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated
    Category: VHDL-FPGA-Verilog Upload User：weiguoqing Size：26K
  • [Others] 4VerilogFIFO.rar FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated
    Category: VHDL-FPGA-Verilog Upload User：dalishi Size：3K
  • [Others] circularbuffer.rar Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.
    Category: VHDL-FPGA-Verilog Upload User：changying Size：1K
  • [Others] 89_full_adder.rar full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
    Category: VHDL-FPGA-Verilog Upload User：liuyao403 Size：5K
  • [Others] taix_fee.rar verilog HDL prepared Taxi Accounting System
    Category: VHDL-FPGA-Verilog Upload User：fp99766 Size：541K
  • [VHDL] USB_jtag.zip Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.
    Category: VHDL-FPGA-Verilog Upload User：jingce008 Size：1535K
  • [VHDL] VERILOGHDLlanguage.rar verilog HDL language, for ultra-large-scale integrated circuits are very beneficial to the development of learning
    Category: VHDL-FPGA-Verilog Upload User：hoffmann Size：2860K
  • [Others] key.rar Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a ...
    Category: VHDL-FPGA-Verilog Upload User：abc7109 Size：2150K