-
-
[
VHDL]
clkconv.rar
A convenient all-digital clock frequency conversion circuit design, do not use PLL, stall converter, and its resources are less occupied.
-
-
[
Others]
The-parameter-design-of-the-digital-phase-lock-loo
For how to design the parameters of the digital PLL helpful. Analysis of the minimum noise equivalent bandwidth, minimum-phase mean-square error, as well as the minimum lockout time of three within the meaning of parameter optimization design
Category:
Document Upload User：
qiuqixian Size：
81K
-
[
Matlab]
pll-linear.rar
The program describes the second-order PLL loop filter design and linear model analysis
Category:
matlab Upload User：
rcpipe Size：
1K
-
-
[
C/C++]
DEC6713_SBSRAM.rar
sbsram test procedures, including the 6713 and the EMIF pll configuration, development environment for CCS
-
[
C++ Builder]
PLL.zip
PLL control IC is used AT89C2051, using P1 control I do, I do not know you have no interest
-
[
Matlab]
simulink_labs.rar
... the Simulink files (*. mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation. The idea here is to implement experiments of a traditional ...
-
[
C/C++]
DSPdriver.rar
DSP interface startup configuration file, including DDR, Pll, GPIO and other parts of
-
[
C/C++]
DSPprog.rar
DSP2808 routines. TMS320F2808DSP the various modules of the application of routines, including the SCI, PWM, AD, CAN, PLL, etc.
切换至中文 Over 1 million code package, 10 million code file free download 
