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PDF]
User_manual_2410x.zip
... Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen
Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface,
2-ch SPI and PLL for clock generation.
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[
VHDL]
593352pll.rar
Prepared by the use of VHDL digital PLL, the FPGAzhong would like flexibility in the use of the clock to help the people.
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[
PDF]
Mod-Demod-FM.rar
it is and Modulator and Demolator on FM, it helps you to build it with a VCO and a PLL LM565
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[
PPT]
Stability.rar
Stability of linear methods of synchronization status of the fully connected network of PLL
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[
VHDL]
Modelsim6.0PLL.rar
modelsim6.0 PLL simulation steps can be used for functional simulation and timing simulation
Category:
IT Hero Upload User：
khetyn Size：
206K
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[
Matlab]
simulink_labs.rar
... depth by giving you
the reins to play with it ! It contains the simulink files (*.mdl) which are block design
files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital
Data Transmission, PCM and Delta Modulation.
Category:
matlab Upload User：
gljknet Size：
1975K
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[
C/C++]
ADF4360-7(350-1800).rar
... count. It can be used to generate system clock, as a test equipment for wireless local area network (LAN), as a closed-circuit television (CATV) equipment. ADF4360-8EB1 evaluation board allows users to assess the ADF4360-8 Synthesizer PLL performance.
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