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03034.rar
verilog of a state machine and no decisive function could achieve multiple functions assigned to the case, you want to help.
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VCDwtHDLV.rar
<Large RISC processor design- Verilog design language used to describe VLSI chip>> CD-ROM
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PDF]
memoryuse.rar
Verilog HDL language in the FPGA memory of the use of detailed
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Perl]
vtopgen.rar
[original] generation sub-module of the top verilog paper documents, automatically complete module interconnection. Reduce the tedious redundancy of labor. Raise working efficiency.
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C/C++]
i2cjiekouchengxu.rar
IIC interface procedures, Xia Wen is the book series "verilog Digital System Design Guide," the IIC the source, very user-friendly
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verilogzzhwfy.rar
QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
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TEXT]
sdr_data_path.rar
SDRAM controller member Verilog code, data link module, Top module completed and the data exchange