verilog code resource search result, page 97, Verysource

[Others] SystemOfTaxiFeeBasedOnVerilogHDL.rar ... and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic ... to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ ...
Category: VHDL-FPGA-Verilog Upload User：jidafenti Size：207K
[Others] VerilogHDLDigtialSystemDesign.rar Verilog HDL digital design and synthesis Xia Wen translation (second edition)
Category: VHDL-FPGA-Verilog Upload User：szjrhb Size：526K
[Others] FromAlgorithmToAchievmentOfHardware.rar From algorithm design to hard-line Verilog HDL logic realize cattle were prepared by the classic book, which contains many examples
Category: VHDL-FPGA-Verilog Upload User：caitao Size：811K
[Matlab] oneperiod.rar Will be sinusoidal segmentation, digital processing, that is, dds technology, ready to do for the Verilog
Category: VHDL-FPGA-Verilog Upload User：whwddz88 Size：3K
[Others] fifo.rar The use of Verilog language, the FPGA configuration into a fifo
Category: VHDL-FPGA-Verilog Upload User：gangqiang Size：19K
[Visual C++ (VC++)] ocidec3.rar IDE of the Verilog design, has been verified.
Category: VHDL-FPGA-Verilog Upload User：liuxx2 Size：26K
[Others] cpu.rar RISC cpu, using Verilog prepared and detailed tutorial
Category: VHDL-FPGA-Verilog Upload User：xfltan Size：210K
[MultiPlatform] sine.rar Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Category: VHDL-FPGA-Verilog Upload User：jsgjzzgs Size：102K
[Perl] Perlilog-0.3.tar.gz Automatic generation of Verilog tools
Category: VHDL-FPGA-Verilog Upload User：fangxd957 Size：47K
[Windows_Unix] RISC_Core.ZIP This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
Category: VHDL-FPGA-Verilog Upload User：tlw1395 Size：333K

keyword: verilog