verilog code resource search result, page 53, Verysource

[Visual C++ (VC++)] SPI_FireWall.rar verilog spi file with testbench
Category: VHDL-FPGA-Verilog Upload User：youhan Size：48K
[Visual C++ (VC++)] VCchuankou.rar verilog ADPLL file with testbench
Category: VHDL-FPGA-Verilog Upload User：wuzhanrong Size：27K
[Others] synthesizable_Verilog_syntax_and_semantics.rar synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.
Category: VHDL-FPGA-Verilog Upload User：szwy2007 Size：292K
[Others] jiaotongdeng_Verilog.rar traffic signal controllers and It is a subject design report, written in verilog, quartus ii environment, and can be used with reference.
Category: VHDL-FPGA-Verilog Upload User：yhsy5188 Size：293K
[VHDL] SPIBusVerilog.rar SPI serial bus interface Verilog realization elaborate on the realization of the process.
Category: VHDL-FPGA-Verilog Upload User：hoho1980 Size：389K
[VHDL] LDPC_Behavioral_VHDL.rar Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
Category: VHDL-FPGA-Verilog Upload User：sztoby7 Size：2K
[C/C++] FPGApro.rar verilog HDL actual industrial projects source development tools altera quartus2
Category: VHDL-FPGA-Verilog Upload User：xq2006 Size：1201K
[VHDL] Verilog_HDL.rar Pioneer studio out of Verilog HDL design and verification
Category: VHDL-FPGA-Verilog Upload User：bjhxlaser Size：14406K
[VHDL] adder.rar cpld/fpga common adder Verilog design procedures
Category: VHDL-FPGA-Verilog Upload User：nnpulika Size：2K
[VHDL] RSdecoder.rar cpld/fpga RS (204,188) decoder of the Verilog program
Category: VHDL-FPGA-Verilog Upload User：lvp1979 Size：13K

keyword: verilog