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  • [Others] source9-10.rar Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
    Category: VHDL-FPGA-Verilog Upload User:jinglongcn Size:15K
  • [Others] source11-12.rar Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
    Category: VHDL-FPGA-Verilog Upload User:hefei6623 Size:9K
  • [MultiPlatform] 9.16fifoasi.rar the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
    Category: VHDL-FPGA-Verilog Upload User:riches851 Size:2697K
  • [Others] uart_verilog.zip include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
    Category: VHDL-FPGA-Verilog Upload User:fp99766 Size:9K
  • [MultiPlatform] fpga1394.rar This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.
    Category: VHDL-FPGA-Verilog Upload User:hnrcjx Size:3K
  • [VHDL] HwLog10.rar It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.
    Category: VHDL-FPGA-Verilog Upload User:twequb555 Size:13K
  • [VHDL] cordic.rar CORDIC FPGA using the Verilog procedures realize
    Category: VHDL-FPGA-Verilog Upload User:ledzyb Size:2K
  • [VHDL] Microprocessor.rar Verilog HDL language proficiency of a good cpu code
    Category: VHDL-FPGA-Verilog Upload User:liaobsh Size:756K
  • [VHDL] CPLDtemperatureinthefiredetectionsystemof.rar ... of Fiber Bragg Grating temperature fire detection system principles, and focuses on the use of CPLD design virtual MC14499 device module, are given and explained using the Verilog HDL language to achieve some of the procedures and simulation test results.
    Category: VHDL-FPGA-Verilog Upload User:xionggy Size:338K
  • [VHDL] crc_d8.rar Verilog module containing a synthesizable CRC function //* polynomial: (0 1 8) //* data width: 8
    Category: VHDL-FPGA-Verilog Upload User:mt3889898 Size:1K