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keyword: PLL

  • [VHDL] ad_clk_pll.rar phase-locked pll of fpga design, altera devices EP1s25 selection, design
    Category: C++ eBooks Upload User：dcjazfp Size：3K
  • [VHDL] adsx.rar phase-locked pll of fpga design, altera devices EP1s25 selection, design
    Category: VHDL-FPGA-Verilog Upload User：hkhuiyang Size：2K
  • [VHDL] fast_pll.rar phase-locked pll of fpga design, altera devices EP1s25 selection, design
    Category: VHDL-FPGA-Verilog Upload User：weigute Size：3K
  • [VHDL] pfl_d.rar phase-locked pll of fpga design, altera devices EP1s25 selection, design
    Category: VHDL-FPGA-Verilog Upload User：dibai_tech Size：3K
  • [VHDL] ad_pll.rar phase-locked pll of fpga design, altera devices EP1s25 selection, design
    Category: VHDL-FPGA-Verilog Upload User：hz881225 Size：3K
  • [Matlab] pll_acsidefilter.zip PLL AT AC SIDE FILTER
    Category: matlab Upload User：richteam Size：9K
  • [VHDL] clock.rar By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
    Category: VHDL-FPGA-Verilog Upload User：pipelchina Size：197K
  • [Windows_Unix] Cy3672.zip CY3672 Cypress PLL calcuration tool.
    Category: Windows Develop Upload User：lit4055 Size：391K
  • [C/C++] PLL_init.rar Pll Busclock to 40M for S12X MCU~
    Category: SCM Upload User：bjjhmcc Size：2K
  • [C/C++] MC145162.rar A very practical PLL drive. Chip for the MC145162. This is a four-lane drive, compared to the three-to twice as fast as, oh
    Category: CSharp Upload User：boli770 Size：14K