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keyword: DDR

  • [Others] leon3-altera-ep2s60-ddr.rar The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor ...
    Category: Graph Drawing Upload User：qdrintftf Size：101K
  • [Visual Basic (VB)] ddr.zip This is a revolution of the source
    Category: Compress-Decompress algrithms Upload User：xingang02 Size：400K
  • [Visual C++ (VC++)] ddr.rar 实现停车场管理与计费功能,可以实现单项停车场的停车管理与计时收费功能！
    Category: Windows Develop Upload User：adriana Size：2K
  • [Visual Basic (VB)] VBtiaowuji.rar DDR VB source code of the simulation program. . . . . . . . . . . .
    Category: Windows Develop Upload User：qdlite Size：401K
  • [TEXT] ref-ddr-sdram-verilog.zip sdram verilog source code realizes
    Category: Embeded-SCM Develop Upload User：zhongxx05 Size：883K
  • [Others] ddr.rar I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
    Category: VHDL-FPGA-Verilog Upload User：cqlm8888 Size：2K
  • [Asm] EEPROM24CXX.rar EEPROM qi application for reference to the District EEPROM data read out (current value = A DDR WRC_
    Category: SCM Upload User：wrf_2007 Size：1K
  • [Others] xapp858[1].Rar ... DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input/Solution Series ( ...
    Category: VHDL-FPGA-Verilog Upload User：scene123 Size：291K
  • [Others] very-good-ok-ref-ddr-sdram-verilog.zip Sdr SDRAM controller reference design, very good
    Category: SCM Upload User：zhangyitnt Size：875K
  • [Visual C++ (VC++)] xapp858.zip Xilinx DDR to achieve the company s source code, and they hope to be helpful to your development
    Category: VHDL-FPGA-Verilog Upload User：mui6336 Size：64K