DDR code resource search result, page 10, Verysource

[C/C++] EVMDM6437ddrtest.rar the EVMDM6437_ddr_test can test the one of both the chip of ddr on the board.
Category: Embeded-SCM Develop Upload User：czyzy98 Size：1K
[Unix_Linux] nandboot.rar mx27 bootloader nandboot cpu:i.mx27 nand:K9F2G08U0A ddr:HYB18M1G320BF-7[1][1].5
Category: Embeded Linux Upload User：nttfjj Size：92K
[Visual C++ (VC++)] 1.rar PCIE and the DDR interface examples provided by the altera
Category: Embeded-SCM Develop Upload User：wpprain Size：255K
[VHDL] yuqix_datum.rar ... I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese . DDR SDRAM control the timing analysis based on the model. Pdf
Category: VHDL-FPGA-Verilog Upload User：tjw963852 Size：20498K
[C/C++] ddr.rar the text is for the davinci .
Category: DSP program Upload User：syj200512 Size：83K
[PDF] c_xapp260.zip ... explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device ...
Category: VHDL-FPGA-Verilog Upload User：zhxjdc Size：1097K
[VHDL] c_xapp851.zip ... application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read ...
Category: VHDL-FPGA-Verilog Upload User：jyyoga2006 Size：399K
[Others] ddr_verilog_xilinx.rar xilinx' s original source code of the DDR timing control.
Category: VHDL-FPGA-Verilog Upload User：lilian968 Size：665K
[PDF] DDRSDRAMcontroller.rar DDRⅡ+SDRAM　ｃｏｎｔｒｏｌｌｅｒ.rar
Category: Document Upload User：biaote1 Size：2592K
[VHDL] rtl.rar ddr controller in verilog...............
Category: VHDL-FPGA-Verilog Upload User：slh168 Size：68K

keyword: DDR