切换至中文 Over 1 million code package, 10 million code file free download
  • [Others] LED47DISP.rar 4-7segment led display Verilog code. Impl emented at Stratix EP1S25 DSP development boar d.
    Category: VHDL-FPGA-Verilog Upload User:kvexpo Size:2K
  • [Others] blocking.rar verilog language based on the data selector, including data selection for the test module
    Category: VHDL-FPGA-Verilog Upload User:cdsltjy Size:28K
  • [MultiPlatform] memoryverilog.rar one of the original Memory design code prepared by the use of verilog we hope to help some
    Category: VHDL-FPGA-Verilog Upload User:sxdline Size:26K
  • [Others] half_clk.rar verilog prepared with moderate frequency divider and another test procedures
    Category: VHDL-FPGA-Verilog Upload User:gydzd3 Size:21K
  • [Others] fdivision.rar verilog prepared with moderate frequency divider and another test procedures
    Category: VHDL-FPGA-Verilog Upload User:lcjinde Size:26K
  • [Others] hmac-zy.rar hmac the verilog code word through the control options or hmac sha1 Operational Operational
    Category: VHDL-FPGA-Verilog Upload User:coco_lee Size:546K
  • [Others] VerilogHDLjihe.rar guo Verilog HDL procedures set includes all commonly used procedures
    Category: VHDL-FPGA-Verilog Upload User:wxjjkj Size:111K
  • [PDF] Synthesisofverilog.rar a useful comprehensive Verilog language study
    Category: VHDL-FPGA-Verilog Upload User:ronchen Size:266K
  • [Others] 9.1_ONE_PULSE.rar based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by ... detailed description and simulation of 9.1. 6 functional modules Verilog-HDL description of the modular input method detection module 9.1 ...
    Category: VHDL-FPGA-Verilog Upload User:salesceo Size:4K
  • [Others] 9.2_LCD_PULSE.rar based on Verilog-HDL hardware Circuit of 9.2 LCD display module with the series Single-Pulse Generator 9.2.1 LCD display module Principle 9.2.2 shows the logic design Thinking and Process 9.2.3 LCD display module hardware 9.2.4 programmable single pulse ...
    Category: VHDL-FPGA-Verilog Upload User:xjhday Size:5K