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  • [Visual C++ (VC++)] MEASURE.rar This program is a simple Measurement Recorder. It is based on the LPC CPU and records the state of Port 1 and Port 2
    Category: ARM-PowerPC-ColdFire-MIPS Upload User:qzshengrun Size:4K
  • [C/C++] GumballStateWinner.rar A small gambling procedures, the main source of this process can give you a design model, called the state design pattern.
    Category: Other windows programs Upload User:firstzhw Size:7K
  • [Others] SDMX512appg.rar ... , a large number of people using the DMX512 control protocol, it is by the United States Association of Theater Technology (United State Institute for Theatre Technology, Inc) in August 1986 proposed a in a pair of 512-line transmission path SCR dimming ...
    Category: Communication Document Upload User:starbao520 Size:160K
  • [Visual C++ (VC++)] ss.rar state-space model used for wind turbine simulations
    Category: Windows Develop Upload User:lis3115 Size:1K
  • [Matlab] Adaptive_Turbo_coded_OFDM.rar ... have some reference value.- Adaptive turbo-coded OFDM, Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State university in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering.
    Category: Other eBooks Upload User:qjd158 Size:593K
  • [VHDL] rc5_enc.rar RC5 of encryption, with state machine, a total of four state st_idle, st_ready, st_round_op, st_pre_round
    Category: VHDL-FPGA-Verilog Upload User:judyxu8507 Size:2K
  • [VHDL] inverter.rar RC5 of decryption, with the same state machine, the same four state
    Category: VHDL-FPGA-Verilog Upload User:hygs118 Size:2K
  • [VHDL] RC5_inv.rar State machine without the decryption of rc5
    Category: VHDL-FPGA-Verilog Upload User:xagelinge Size:2K
  • [Matlab] zishiyingjunheng.rar ... , channel estimation algorithm. The BER results are determined through Monte Carlo simulation. The demo shows how to use these equalizers seamlessly across multiple blocks of data, where equalizer state must be maintained between data blocks.
    Category: matlab Upload User:jane775 Size:100K
  • [VHDL] DE2_VGA3.zip ... generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
    Category: VHDL-FPGA-Verilog Upload User:hooadolf Size:1247K