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  • [Visual C++ (VC++)] simulationofairport.rar day simulation of an airport of aircraft taking off and landing aircraft landed issue the priority level higher than the take-off priority
    Category: OpenGL program Upload User:hollekit Size:2K
  • [Visual Basic (VB)] StockTrade.zip Stock Exchange simulator to show timers and randon number generators work together. A cool simulation for anyone who might think about playing the stocks and spending money and get a general idea how the system works.
    Category: Finance-Stock software system Upload User:apthhl Size:8K
  • [Visual C++ (VC++)] Bank_Accou18338212272004.zip ... a database which holds records for bank account records. It is not a simulation of what you would see at an ATM machine but it would be a simulation of a bank administrator. You have the capability of entering records such as Checking ...
    Category: Windows Develop Upload User:rifeng33 Size:54K
  • [C#(.net)] CSharp_MATLAB.zip matlab and C# interoperability programming. proficient in C# for the comrades, simulation of very complex procedures, if they can be called directly MATLAB has a function that will be the realization of this paper c# function call Matlab
    Category: E-Books Upload User:chenyang Size:19K
  • [C/C++] ECE348_Lab1_shah006.zip To learn how to use MPLAB Integrated Development Environment (IDE) for code generation, simulation, and debugging. This code is a very simple program that sets up PORTC and PORTB I/Os and sends some values over these ports, and tries to read Port C and ...
    Category: assembly language Upload User:zslchong Size:420K
  • [Windows_Unix] OFDM_4QAM.zip OFDM 4QAM simulation using Matlab
    Category: Communication-Mobile Upload User:jomhr2008 Size:58K
  • [Windows_Unix] timing_recovery.zip OFDM simulation for timing recovery
    Category: Communication-Mobile Upload User:ricardo81 Size:116K
  • [VHDL] McGraw.Hill.VHDL.Programming.by.Example.4th.Ed.ra ... process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called At-Speed debugging that provides extremely fast design ...
    Category: Other eBooks Upload User:xwei13689 Size:1743K
  • [VHDL] Advanced.ASIC.Chip.Synthesissys.rar ... for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At ...
    Category: E-Books Upload User:bjuv365 Size:2192K
  • [Matlab] 1_mmc_inf.rar Simulation model of a single server queue
    Category: Fax program Upload User:popdiy Size:7K