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[
PDF]
code_coverage.rar
... the design verification process. It is essential, therefore, that you have confidence your testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.
Category:
SCM Upload User：
bdhydg Size：
727K
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[
PDF]
Vhdl_Simulation_With_Modelsim.rar
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of
designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
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[
Matlab]
RS_BCH.zip
... liu
Summary: simulation of binary and non-binary bch decoder
MATLAB Release: R14SP1
Required Products: Communications Toolbox
Description: simulation of binary bch decoding algorithm for bch(n, k) with t bits error correction capability.
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matlab Upload User：
sdlierk Size：
0K
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[
C/C++]
itpp-3.10.12.tar.gz
IT++ is a C++ library of mathematical, signal processing and communication system routines/functions. Its main use is in simulation of communication systems or for performing research in the area of communications.
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[
Matlab]
baham1.rar
Induction motor matlab simulation in simulink with and without core loss effetct are attached
Category:
matlab Upload User：
wjt008 Size：
9K
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[
Matlab]
Simulation.rar
MATLAB based on the viterbi encoding, decoding simulation program
Category:
matlab Upload User：
jyhhlqq Size：
10K
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[
Java/JSP]
multicast.rar
P2P Streaming vs. File Downloading
Introduction to PlanetLab and Simulation
A Survey
CoopNet
Promise/CollectCast
Dagster
Our approach
Flow Simulators
Category:
P2P Upload User：
d81209 Size：
3K
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[
Others]
lc2.zip
... from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a ...
Category:
SCM Upload User：
huhao316 Size：
42K
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[
Others]
DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)
... . We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this ...
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