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[
VHDL]
DCT.rar
altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
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[
VHDL]
asynch_fifo.rar
FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
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[
VHDL]
an_dcfifo_top_restored.rar
alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
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[
VHDL]
hamingFPGA.rar
This article describes the Hamming encoding and decoding through the FPGA device to implement, introduced the use of VHDL programming language is the basic algorithm!
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