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[
VHDL]
crc_7GPGA.rar
Using FPGA to achieve CRC algorithm, only one pulse will be able to realize, than the traditional algorithm greatly saving time shift
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[
VHDL]
pll.rar
Using FPGA digital phase-locked loop, development environment for ISE
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[
VHDL]
FPGAbi_ioreseach.rar
: For field programmable gate array (FPGA) chip features of FPGA in the bi-directional port I/O design, the simulation is initialized at the same time two-way port I/O method. Using this design method of two-way ports, optional Spartan2E the Xilinx chip ...
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[
VHDL]
AlteraFPGA.rar
altera several new FPGA configuration methods and the use of experience
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[
VHDL]
200808.rar
Single-chip serial communication with the FPGA source code, very useful Oh
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