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[
MultiPlatform]
RS_Euclid_FPGA.rar
RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder
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[
MultiPlatform]
GF_2_m_FPGA.rar
Domain multiplier GF_2_m_ rapid design and FPGA realization for rs wing made the understanding of code and design has helped
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[
VHDL]
CLOCK.rar
FPGA-based multi-functional electronic clock designs are very classic Oh
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[
Others]
iicmainrd_32.rar
Use FPGA to come ture the main control of the iic comunication, the most simple code and using the least FPGA resource
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[
Others]
uart_verilog.zip
include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.