design code resource search result, page 46, Verysource

[C/C++] analog432.rar to C2051 microcontroller core, using TLC2543 12 serial A/D converters, Design of a serial data collection/transmission module provides the hardware schematic and source code
Category: Project Design Upload User：aphexiang Size：26K
[Windows_Unix] LabVIEW-DAQdll.rar an excellent article! Domestic AD card dynamic link library design and virtual instrument with the appropriate platform for LabVIEW Distribution methods
Category: Project Design Upload User：eeddtt Size：118K
[Windows_Unix] ADSPTS201MULTIPROCESSORSYSTEM.rar This is an overview of ADSP Tiger sharc TS201 multiprocessor system design.
Category: Other eBooks Upload User：clickwh Size：257K
[VHDL] xapp345_verilog.zip IrDA & UART Design (Verilog)
Category: Com Port Upload User：huazheng02 Size：10K
[Java/JSP] J2EEDesignPatterns.rar creates design pattern, classic material
Category: Java Develop Upload User：john_nb Size：1183K
[Others] CLOCK_co-design_of_C_and_Verilog.rar A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
Category: Other systems Upload User：yisteven Size：37K
[Others] Net-based.rar Personalized learning environment for network design principles and realization of Design Principle and Practice of Personalized Net-basedLearning Environment
Category: Windows Develop Upload User：yf_shq Size：1059K
[Others] 123.rar Personalized Web-based self-learning platform design Design of the Personalized Self-determinedLearning of system based on network
Category: Windows Develop Upload User：ggx1231 Size：1921K
[Others] Find_medium_value_co-design_of_C_and_Verilog.rar A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
Category: Other systems Upload User：liaoyt_253 Size：11K
[Others] Traffic_sign_co-design_of_C_and_Verilog.rar This is an extension of sign example. You can design your own traffic sign by using Verilog. And the result from Verilog can be seen by the attached C file.
Category: Other systems Upload User：hr2818 Size：254K

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