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  • [VHDL] ram_sp_sr_sw.zip ROM using file.suite in design a simple CPU
    Category: File Formats Upload User:hjf5959 Size:1K
  • [VHDL] ram_dp_sr_sw.zip suite in design a simple CPU
    Category: Development Research Upload User:margaret Size:1K
  • [PDF] Carvc++mapx.rar A use of MapX and vc-board positioning system to develop research, the article detailed the design of automotive systems and MapX correlation function introduced
    Category: Project Design Upload User:nobole Size:157K
  • [Delphi] Borland_Delphi_7_Component_Writers_Guide.zip Overview of component creation This chapter provides an overview of component design and the process of writing components for Delphi applications. The material here assumes that you are familiar with Delphi and its standard components. • Class ...
    Category: Delphi VCL Upload User:asd6397 Size:956K
  • [Java/JSP] java_design_patterns.rar ... off-putting when you first encounter it. But, in fact, design patterns are just convenient ways of reusing object-oriented code between projects and between programmers. The idea behind design patterns is simple-- write down and catalog common ...
    Category: Java Develop Upload User:hydsyy Size:1180K
  • [Java/JSP] calculator.zip Experiment with eclipse calculator functions, it is mvc structure, and is the observer of the design pattern
    Category: Windows Develop Upload User:asli888 Size:10K
  • [Java/JSP] Observer.zip design pattern in the observer, the experimental features of the sort. And graph
    Category: Windows Develop Upload User:liww2001 Size:16K
  • [Visual C++ (VC++)] fyksj.rar a mechanical engineering graduate of the College of Design and very useful Thesis
    Category: Project Design Upload User:heheyougui Size:3120K
  • [Visual C++ (VC++)] shlsji.rar a college graduate thesis and design is very valuable, and worthy of attention
    Category: Project Design Upload User:sdyongqian Size:7170K
  • [MultiPlatform] BoothMultiplier.rar ... -architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
    Category: VHDL-FPGA-Verilog Upload User:lianshensl Size:2K