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  • [VHDL] EXA05.rar VHDL CPLD on the development of experimental procedures, through the use of max+ plus run the program, the experimental implementation-related features
    Category: VHDL-FPGA-Verilog Upload User:lczhongchu Size:92K
  • [Asm] dma.rar dsp5000 Series dma entirely reliable assembly code is available, can be directly downloaded to the dsp, the need to rewrite parameters, has nothing to do with the CPLD configuration
    Category: DSP program Upload User:lxfyzmin Size:29K
  • [VHDL] testt2.rar By the MCU and CPLD together seven digital frequency meter
    Category: SCM Upload User:tzdacheng Size:2K
  • [VHDL] traffic_light.rar CPLD to control the traffic light process, the procedure is pretty good! U.S. study with ah!
    Category: VHDL-FPGA-Verilog Upload User:zcm977230 Size:872K
  • [PDF] CPLDEPM7128A.rar An introduction in English about 7128CPLD, which contains a 44 foot to 100-pin MAX Series all models cpld
    Category: E-Books Upload User:lcjiulong Size:499K
  • [Others] TI_DSP_USB2_XDS510_Emulator.rar ... on the introduction of the DSP simulator development method. Using this method, only the design of DSP hardware emulator system and CPLD program, USB driver design uses TI provides the source code, the simulator is very simple and easy to develop. The ...
    Category: DSP program Upload User:baimudf Size:252K
  • [VHDL] usb_Blaster_rev0.rar USB Blaster for the Altera Corporation for CPLD/FPGA devices introduced high-speed programming
    Category: VHDL-FPGA-Verilog Upload User:nxf106 Size:2087K
  • [VHDL] abs_code.rar This is read by the CPLD Development absolute encoder feedback signal to the code, read the motor' s rotor position and to determine the absolute direction of rotation is very useful for motor control.
    Category: VHDL-FPGA-Verilog Upload User:hszahd Size:1565K
  • [VHDL] manqiesite2_final.rar cpld achieve serial transmission of parallel data transceiver module (category Manchester code). 2M largest parallel rate.
    Category: Embeded-SCM Develop Upload User:w78781658 Size:316K
  • [VHDL] 40caiji.rar The source is based on the CPLD 40 road Digital Signal Acquisition Acquisition submit one set of data and is subject to deal with single-chip single-chip control
    Category: SCM Upload User:jasonliu9 Size:1K