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VHDL]
jtag_logic.rar
USB-Blaster CPLD main program, including the distribution does not include the pin, adding it has made it clear.
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VHDL]
ICX408AL7.5M.rar
CPLD based on the CCD driver source, I have been tested with single-chip control, you can achieve CPLD driver for CCD control and exposure control
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fjxsgc Size：
533K
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Others]
usbblaster.rar
usb-blaster, USB port download CPLD lines, a full set of production data, which has a detailed description
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VHDL]
AIC.rar
The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame ...
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VHDL]
I2C.rar
I2C core code in Hardware descrption language so as enable a cpld/fpga to be programmed for specific customized applications of our requirment & make the pcb work to meet the application requirements.
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VHDL]
serial.rar
... time slots in order to enable synchronous communication.
- Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome"
- String (serial debug tools is set to accept by way of A
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