-
-
[
VHDL]
sd_IP.rar
... SD mode.I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.Good luck
-
[
C#(.net)]
clock.rar
c# development clock procedures. This is the school c# Courses to do a design. The exhibitions!
Category:
CSharp Upload User：
xiexi95566 Size：
12K
-
[
LabView]
Clock(8.2).rar
Super nice clock interface, there is a need to take with you on the hope that everyone likes
-
-
[
C/C++]
fet410_ta.rar
... is set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK. Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off andused only durring TA_ISR. ACLK = n/a ...
-
[
VHDL]
clock.rar
Two buttons control the school at the time of VHDL source clock, alarm clock and calendar with timing function
-
-
[
Asm]
clock.rar
Using assembly language to write procedures for the clock, it is practical. Easy-to-read
-
[
ASP/ASPX(.net)]
asptime.zip
ASPTimeVersion 1.00ASPTime is a stop-clock component for use in ASP pages. It also includes a pause function to pause between events. Keep a look out for updates at www.cs.niu.edu/ ~ z951259/comlinks.html. Thank you for using ASPTime.
-
[
Asm]
clock.rar
asm source code under dos digital clock, see the procedure to use
切换至中文 Over 1 million code package, 10 million code file free download 
