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keyword: bit

  • [Matlab] GAbit_tourney.zip Algorithme genetique bit tourney
    Category: Windows Develop Upload User：ailsa1102 Size：3K
  • [Delphi] UnitCrc.rar CRC 32 bit fixed poly 0x04c11db7 algo unit
    Category: Crypt_Decrypt algrithms Upload User：lv5171 Size：2K
  • [VHDL] Mux5-1.zip Implementation of a 5to1 3-bit Mux
    Category: Windows Develop Upload User：lishijd Size：1K
  • [VHDL] Mux4bit.zip Implementation of a 4-bit mux
    Category: Windows Develop Upload User：zbgqbxg Size：1K
  • [VHDL] Mux2bit.zip Implementation of a 2-bit MUX
    Category: Windows Develop Upload User：uvata003 Size：1K
  • [Matlab] DeformPFMT.zip Code written by Namrata Vaswani. A small part of the code (a little bit of the level set part) is taken from code written by Yogesh Rathi Please cite Namrata Vaswani, Yogesh Rathi, Anthony Yezzi, Allen Tannenbaum, PF-MT with an Interpolation Effective ...
    Category: Special Effects Upload User：ganzaolu Size：105K
  • [VHDL] temperaturedetectSorcecode.rar four bit ripple carry adder
    Category: Windows Develop Upload User：deshengyi Size：5K
  • [VHDL] bitadder.rar verilog code for 4 bit adder
    Category: VHDL-FPGA-Verilog Upload User：arketipo Size：7K
  • [Others] rdvv.rar ... 5 Volt 3 = Supply Voltage LCD Driver 4 = RS, Register Select, Low=Instruction, High=Data 5 = R/W, Read/Write 6 = Enable 7 to 14 = DB0-DB7, Data Bus software selectable 4 or 8-bit mode 15 = LED+ (Anode of LED Unit) 16 = LED- (Cathode of LED Unit)
    Category: assembly language Upload User：yjw001 Size：2K
  • [VHDL] fifo_32_4321.rar Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
    Category: VHDL-FPGA-Verilog Upload User：yashilin Size：5K