bit code resource search result, page 84, Verysource

[VHDL] harshit1.rar 32 bit scalable multiplier architecture
Category: VHDL-FPGA-Verilog Upload User：solove Size：90K
[VHDL] modi3.rar sub nano second 32 bit multiplier
Category: VHDL-FPGA-Verilog Upload User：yzgmmf Size：264K
[C/C++] mcasp_example.rar MCASP example to demonstrate DIT transmission for Q31 24-bit data type
Category: WEB(ASP,PHP,...) Upload User：wangpu06 Size：11K
[Matlab] 80211b-simlink.rar 802.11b simulink simulation source code for PHY layer. It can be used to generate bit-true test vector for RTL level design(FPGA).
Category: Communication Upload User：qdytkj Size：86K
[Visual C++ (VC++)] DLC1.zip This is a network transport layer crc bit stuffer
Category: Crypt_Decrypt algrithms Upload User：wuhaihua88 Size：1K
[Asm] sqrt.rar Find out the square root of the 8-bit number
Category: assembly language Upload User：angelica Size：2K
[VHDL] ALU_32.zip 32 bit ALU design,LU Operations: This input specifies the ALU operation to be used during the acquisition process. The ALU operations are divided into logical operations and two classes of arithmetic operations. The two classes of arithmetic operations ...
Category: Windows Develop Upload User：hezuo009 Size：1K
[VHDL] Counter.zip Counter 8-bit it count 8 bits
Category: Windows Develop Upload User：wzhuarui01 Size：80K
[VHDL] lab5.rar Write a 1 bit of 2-to-1 MUX VHDL code
Category: Embeded-SCM Develop Upload User：teqite Size：120K
[VHDL] lab7.rar In this practice among the profit we can learn to use Hierarchical VHDL code the way to achieve an n-bit future of the ripple-carry adder, and learn to use package.
Category: Embeded-SCM Develop Upload User：dfzmkf Size：81K

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