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[
VHDL]
ptos.rar
... output, no data output high, output format 1100+8 bit+ parity+0011 (stop bit) serial input, parallel output, detect the parity error, whether there is transmission frame for each bit of data transmission errors accounted for 16 clock cycles
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[
Windows_Unix]
FE2d132.zip
Finite element program written by Charles G. Dietz
2D model incorporating grids, beams, and quads
PowerBasic 9.00 (32 bit compiler)
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[
VHDL]
request_arbiter.rar
... Inputs------
//
// DMACSREQ_i-- The 16-bit signal which stores the single request of all the 16 devices
// DMACBREQ_i-- The 16-bit signal which stores the burst request of all the 16 devices
// hclk_i-- Clock signal
// hresetn_i-- Active low Reset ...
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[
Windows_Unix]
ads7870.zip
... ADS7870 are:
/// - Fast SPI interface (up to 20MHz)
/// - 12-bit results
/// - 8 single-ended or 4 differential input ... ,20x gains)
/// - Software or hardware triggered conversion
/// - 4-bit auxiliary digital I/O lines (controlled via serial ...
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