bit code resource search result, page 72, Verysource

[Java/JSP] addison.wesley.design.patterns.java.companion.zip The term “design patterns” sounds a bit formal to the uninitiated and can be somewhat off-putting when you first encounter it. But, in fact, design patterns are just convenient ways of reusing object-oriented code between projects and between ...
Category: Java Develop Upload User：yichuansj Size：1513K
[Matlab] BER_of_BPSK_DS-SS.zip his m-file finds the bit error rate performance of BPSK DS-SS system over (i) AWGN channel and (ii) Slow Rayleigh fading channel corrupted by AWGN. Compare the performance with simple BPSK system.
Category: Communication-Mobile Upload User：mtjhgs Size：2K
[C/C++] mul16.rar 16 bit multiple library for avr uC
Category: SCM Upload User：bjjyzs Size：1K
[VHDL] 16bitalu.rar 16 bit alu using the vhdl it has 16 function perform by control unit with 4 control signal
Category: VHDL-FPGA-Verilog Upload User：lzy75160 Size：979K
[Matlab] kmplot.zip ... AWGN channel. MacKay-Neal based LDPC matrix. Message encoding uses sparse LU decomposition. There are 4 choices of decoder: hard-decision/bit-flip decoder, probability-domain SPA decoder, log-domain SPA decoder, and simplified log-domain SPA decoder.
Category: Communication-Mobile Upload User：zbhjsl Size：4K
[VHDL] D.zip bit append16 VHDL source code
Category: VHDL-FPGA-Verilog Upload User：zgz030900 Size：2K
[VHDL] mult4x4_1.zip There are 4 bit by 4 bit multiplier to give 8 bit product
Category: Windows Develop Upload User：qrh2007 Size：1K
[C++ Builder] CRC.rar CCSDS 16-bit CRC generator and checker demonstration program
Category: Other systems Upload User：zdh9688 Size：3K
[C/C++] EZWencoding.rar The EZW encoder is based on progressive encoding to compress an image into a bit stream with increasing accuracy. This means that when more bits are added to the stream, the decoded image will contain more detail, a property similar to JPEG encoded images ...
Category: Windows Develop Upload User：jortor Size：56K
[C/C++] 143637___fpgas_and_cplds.rar vhdl couter 3 bit and make by vhdl and vhdl
Category: VHDL-FPGA-Verilog Upload User：jiheng88 Size：2062K

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