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VHDL]
PLL.zip
Matlab with VHDL and digital phase-locked loop circuit prepared.
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PPT]
PLL.rar
Practical Phase-Locked Loop Design.rar
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C/C++]
GSM.rar
C8051F020 control monitoring system using GSM module to send and receive data and control messages at any frequency PLL lock
Category:
SCM Upload User：
puterhan Size：
51K
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Others]
CD4060BE.zip
BE4060 PLL Application Notes documents, the English version. The development of the necessary pulse generator.
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SCM Upload User：
xiao730204 Size：
223K
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PDF]
estimatingandintepretatininstantaneousfrequency.ra
... include differentiation of the phase and smoothing thereof adaptive frequency estimation techniques such as the phase locked loop (PLL), and extraction of the peak from time-varying spectral
representations. More recently methods based on a modeling of ...
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C/C++]
875M.rar
This is the single-chip control MB1502 PLL locks to the frequency of 875M, the procedure can be applied to trial
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SCM Upload User：
bjjxbaijia Size：
1K
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VHDL]
dds9851.rar
... -wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of ...
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VHDL]
pll.rar
Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design an all-digital phase-locked loop method, and use complex programmable logic device CPLD to be achieved, given the main ...
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