DDS code resource search result, page 2, Verysource

[Others] DDS.rar DDS detailed introduction of the basic working principle, and gives several commonly used in the actual use of the chip.
Category: SCM Upload User：jnhjj88 Size：1105K
[VHDL] DDS.rar DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method
Category: VHDL-FPGA-Verilog Upload User：freight888 Size：52K
[VHDL] DDS.rar DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is discrete, in the frequency control word change after one clock cycle to go through before a new phase in accordance with the incremental ...
Category: VHDL-FPGA-Verilog Upload User：yongmei12 Size：2047K
[Others] dds.rar Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
Category: VHDL-FPGA-Verilog Upload User：jiulong120 Size：660K
[VHDL] dds.rar Based on VHDL+ FPGA design of the DDS signal has been through mode
Category: VHDL-FPGA-Verilog Upload User：billow188 Size：547K
[VHDL] dds.rar Available is a good DDS frequency synthesis procedures, using VHDL language
Category: VHDL-FPGA-Verilog Upload User：yangchb Size：1043K
[VHDL] DDS.rar DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Category: software engineering Upload User：dwbfcjerry Size：546K
[Others] FPGA--DDS-PhaseMeasure.rar Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °- ...
Category: SCM Upload User：ookkabc Size：1339K
[VHDL] DDS.rar This is a DDS code bepend on FPGA ,it can generate two waves.
Category: Other systems Upload User：sunine Size：9K
[Others] DDS.rar DDS achieved Quartus using IP core provided by altera
Category: VHDL-FPGA-Verilog Upload User：cnledlamps Size：82K

keyword: DDS