DDS code resource search result, page 9, Verysource

[VHDL] dds.rar FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Category: VHDL-FPGA-Verilog Upload User：qianhua Size：1409K
[Visual C++ (VC++)] dds.rar DDS waveform generator can produce the triangular wave, square wave, triangle wave source.
Category: SCM Upload User：bee3560 Size：2K
[Others] DDS.rar ... then, taking into account the limited hardware resources and the accuracy of DDS, the two methods to optimize the process the last of these two ... : the use of these two methods are all effective ways to achieve the DDS waveform stored in the table design.
Category: VHDL-FPGA-Verilog Upload User：cici_chen_ Size：62K
[C/C++] dds.rar DAC0832-based simulation of single-chip low-frequency signals DDS
Category: SCM Upload User：zhengqiweb Size：173K
[C/C++] DDS.rar The procedures for the use of C language to control DDS chips, the verification procedures have been adopted
Category: SCM Upload User：baiyoushuo Size：1K
[PDF] dds.rar To collect some of their articles on the DDS, the main principle on the DDS and how to use DDS to achieve verilog
Category: Project Design Upload User：timho86 Size：3221K
[C/C++] DDS.rar C8051f020 the DDS-based debugging, the chip used for the AD8951
Category: SCM Upload User：whrhdz Size：44K
[VHDL] DDS.rar A simple VHDL implementation of a DDS on Xilinx Spartan 3E Starter Kit development board
Category: VHDL-FPGA-Verilog Upload User：hxf_0101 Size：105K
[VHDL] DDS.rar DDS signal generator, the use of VHDL realization of frequency control word in accordance with changes in output signals of different frequencies, the maximum arrival 10MBPS
Category: VHDL-FPGA-Verilog Upload User：darendoors Size：766K
[VHDL] DDS.rar In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
Category: VHDL-FPGA-Verilog Upload User：zenbor89 Size：343K

keyword: DDS