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[
VHDL]
mcpu_1.06b.zip
MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD- one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code ...
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[
VHDL]
Verilog_PPT.rar
Southeast University Verilog notes Verilog language as CPLD and FPGA development language than VHDL have more advantages in comparison.
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[
VHDL]
FPGA.rar
FPGA/CPLD Tutorial entity, combined with study-related development tools.
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[
VHDL]
CPLD_zhengxuanbofashengqi.rar
To fully simulate the work of DDS chip in after the CPLD output pin connected to the corresponding D/A conversion chip and connected to low-pass filter, will be a very good spin wave is
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[
VHDL]
add128.rar
128-bit address decoder, in the CPLD or FPGA implementation and may
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[
DOS]
SM2100.rar
CPLD-based incremental photoelectric encoder SOPC Manual
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