CPLD code resource search result, page 69, Verysource

[VHDL] switch.rar switch code,for thinx cpld
Category: VHDL-FPGA-Verilog Upload User：ljhjerry Size：111K
[VHDL] CPLDVHDL.ZIP.zip Based on CPLD and VHDL design of electronic locks, Thesis of the PDF format, you can refer to
Category: VHDL-FPGA-Verilog Upload User：pop121 Size：189K
[VHDL] LCD.rar LCD Interface Xilinx CPLD
Category: VHDL-FPGA-Verilog Upload User：xxthzd Size：1932K
[Others] CPLD_UART.rar FPGA CPLD-based Design and Implementation of UART, a name, we know that you do not say any more,
Category: Embeded-SCM Develop Upload User：piaoyao002 Size：1K
[VHDL] SY10.rar The musical performance circuit’s design and implement Abstract: This paper introduced CPLD／FPGA programmable logic device, development entironment MAX+PLUSⅡ,hardware description language HDL which are related to the musical performance.And this paper ...
Category: VHDL-FPGA-Verilog Upload User：asizhong Size：300K
[VHDL] music.rar Mainly music-based method cpld with a ppt, documents, and the chip description
Category: VHDL-FPGA-Verilog Upload User：zsxcs18 Size：648K
[VHDL] liushuideng.rar Lights to achieve water use verilog for cpld platform has been successful simulation
Category: assembly language Upload User：szjqxwj Size：12K
[Visual Basic (VB)] VHDL_FPGA_FILTER.rar Design using VHDL language FPGA devices based on high sampling rate FIR filter, based on VHDL and CPLD devices, the design of FIR digital filter
Category: VHDL-FPGA-Verilog Upload User：ppv123 Size：892K
[QT] clk_div.rar VHDL language description, the clock frequency, a given CPLD experiment board system clock set 50M, but as a result of this work, we will be the system clock frequency after 20 hours of work needed to be DS18B20 clock, about 1.25M.
Category: VHDL-FPGA-Verilog Upload User：lovezxd444 Size：158K
[C/C++] 1.rar Physical DMA for high-speed data acquisition circuit to achieve the CPLD
Category: Embeded-SCM Develop Upload User：luxi500 Size：104K

keyword: CPLD