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  • [C/C++] mdefir2.rar frequency sampling method used FIR filter design.
    Category: Communication-Mobile Upload User:ybbthppl Size:2K
  • [VHDL] plj.rar Such as precision digital frequency of a project- including VHDL source code and compile the relevant documents after
    Category: VHDL-FPGA-Verilog Upload User:keheng Size:1795K
  • [C/C++] 4_3.rar The use of dynamic scanning and Timer 1 in the digital control to show from the beginning of 765,432 to 1/10 seconds until the speed of descending down 765,398 and maintain display this number, at the same time the use of Timer 0 to 500ms the speed of ...
    Category: SCM Upload User:dgalxgs666 Size:2K
  • [C/C++] 2007.9.7.rar Program-controlled filter papers. To realize a step from 0 to 60dB in 10dB of adjustable gain. Filter part of programmable switched capacitor filter MAX262 chip as the core, realize the cut-off frequency 1Hz step 1KHZ-20KHZ program adjustable filter, the ...
    Category: Communication-Mobile Upload User:dengqunqun Size:107K
  • [C/C++] Real_izing_A_Design_of_Programmed_Control_Have_Fil In cable television in the realization of program-controlled active filter design. In order to make full use of equipment and transmission lines, the need for a frequency selective network- filter, the same lines separate different signal in the TV also ...
    Category: SCM Upload User:aybzybz Size:215K
  • [Asm] Frequencyofprocedure.rar Assembler, using 1602 single-chip LCD digital frequency meter
    Category: SCM Upload User:szttyz Size:4K
  • [C/C++] jiang.rar Frequency counter program, with the 1602 liquid crystal display, and a maximum of seven for, there are three stalls
    Category: Embeded-SCM Develop Upload User:origingem Size:1204K
  • [Matlab] sefade.rar Used to produce frequency selective channel One fade.m can used to generate Rayleigh Fading Channels.
    Category: Mathimatics-Numerical algorithms Upload User:yixiu931 Size:2K
  • [Visual C++ (VC++)] FD_V_Control.rar Serial Port class through the use of 485 interface to the Emerson TD1000 start-stop frequency converter to set
    Category: Communication Upload User:cnzhishi Size:1907K
  • [VHDL] dds.rar dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
    Category: VHDL-FPGA-Verilog Upload User:jxhj88 Size:1061K