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  • [Others] Fre_labview.rar LabView platform frequency calculations show procedures, through the serial port to receive the next bit plane data, and frequency measurement process control, complete the calculation and display.
    Category: LabView Upload User:szvtasmt Size:584K
  • [C/C++] tea5767_3wire.rar TEA5767 the 3-wire control procedures, M8 MCU, using 3-wire control with a circuit schematic can be manually specified frequency, can also be upper and lower search
    Category: SCM Upload User:sjh1581 Size:31K
  • [C/C++] 6bit_cymometer.rar 6-bit digital tube display of the frequency counter, the external square wave received P3.4 (T0), the test
    Category: SCM Upload User:jjiangjuan Size:13K
  • [Matlab] DDS.rar Direct frequency synthesizer simulation source code, hope someone can use to.
    Category: SCM Upload User:nigerwu Size:10K
  • [Others] key.rar Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a ...
    Category: VHDL-FPGA-Verilog Upload User:abc7109 Size:2150K
  • [Matlab] impulse_synthetic1.rar SIAR system based on pulse-integrated MATLAB program, the array model is the launch array element 19, the receiver array elements 40, distributed in three rings, the signal is linear FM signal, plus the Doppler frequencies.
    Category: matlab Upload User:addzjx Size:1K
  • [C/C++] S35390A_C.rar err
    Category: SCM Upload User:rong926 Size:1463K
  • [Others] ddfsdemo.rar Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, ...
    Category: VHDL-FPGA-Verilog Upload User:xfyxliu Size:632K
  • [VHDL] vhdl.rar Frequency counter using vhdl implementation is presented using vhdl achieve precision measurements such as frequency of system design.
    Category: VHDL-FPGA-Verilog Upload User:lixing06 Size:101K
  • [VHDL] dds_gen.rar FPGA-based phase adjustable frequency DDS signal generator
    Category: VHDL-FPGA-Verilog Upload User:malianhui Size:5K