切换至中文 Over 1 million code package, 10 million code file free download
  • [Others] ex7_CAN.rar ... on left foot Right on point, Load GEL, select LF2407.gel, then the menu bar Gel-> LF2407-> CAN regs, you can see the CAN register variables are displayed in the Watch Window Island. CANBOX0 can be seen inside receive data 0x2211, 0x4433 and other d
    Category: SCM Upload User:xmlisimon Size:26K
  • [Matlab] RGB_avi.rar Run RGB Video and watch the R-G-B Video Components parralel to the original Video
    Category: matlab Upload User:sepbadi Size:606K
  • [Asm] timersaat.rar Example program with AVR assembler. Purpose: Education->Assembler->Simple Watch ATMega8 and 1 relay. Relay will be on after 7day:00hour:00minute:00 second after power on. Coded by Basri KUL (I Coded it my microprocessor classes)
    Category: SCM Upload User:sbochun Size:2K
  • [Visual Basic (VB)] clock_with_alaram.rar This is of a small analog model clock with alarm and stop watch
    Category: Windows Develop Upload User:jhniuniu Size:22K
  • [C/C++] tawnhaoqiangCword.rar ... 11 1.13.6 Compile menu 12 1.13.7 Project menu 13 1.13. 8 Options menu 14 1.13.9 Debug menu 18 1.13.10 Break/watch menu 19 1.13.11 Turbo C 2.0 of the configuration file 20 C Language Tutorial C language overview of the development of C language C Language
    Category: Windows Develop Upload User:y440e3 Size:684K
  • [C/C++] watchdog_TIME.rar Texas Instruments new DSP TMS320C2834X watchdog chip SCI WATCH DOG programming.
    Category: DSP program Upload User:cykelida Size:3K
  • [Visual C++ (VC++)] stopwat.zip A stop watch, date and time will be (12KB). Function is complete, VC of the classic examples of programming.
    Category: C++ eBooks Upload User:fuwangsy Size:12K
  • [VHDL] Dongho.rar files describe a example watch : minute and second
    Category: VHDL-FPGA-Verilog Upload User:testhan Size:225K
  • [Visual C++ (VC++)] pocketwatch.zip pocket watch program for the Open GL applications
    Category: OpenGL program Upload User:tjzhitai Size:335K
  • [VHDL] Pld_lab4.zip stop watch in vhdl using MAXII development board.
    Category: VHDL-FPGA-Verilog Upload User:zhanjinxin Size:1K