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keyword: vhdl

  • [VHDL] CPLDexperiment.rar In this study, selected Xilinx tutorial products X9572, with supporting the development of software for ISE4.1i, schematic can be input and VHDL hardware description language input, and can use Modelsim functional simulation and timing simulation.
    Category: VHDL-FPGA-Verilog Upload User：wenyuanie Size：571K
  • [VHDL] LCDshow.rar VHDL based on the LCD display program, including complete source code, locking pin, as well as download files documents can be directly downloaded using
    Category: VHDL-FPGA-Verilog Upload User：like75 Size：19K
  • [VHDL] autosellmachine.rar VHDL-based vending machine realize that contains the complete source code, locking pin, as well as download files documents
    Category: VHDL-FPGA-Verilog Upload User：cqhema1 Size：14K
  • [VHDL] RS232.rar VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using
    Category: VHDL-FPGA-Verilog Upload User：jnydjx Size：16K
  • [VHDL] lcd240128_ok.rar VHDL-based display program in 1602, contains the complete source code, locking pin, as well as download files documents can be directly downloaded using
    Category: VHDL-FPGA-Verilog Upload User：hj5117 Size：775K
  • [VHDL] answermachine.rar Answer Based on the VHDL program, including complete source code, locking pin, as well as download files documents can be directly downloaded using
    Category: VHDL-FPGA-Verilog Upload User：anpa847 Size：9K
  • [VHDL] uart(Verilog).rar UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
    Category: VHDL-FPGA-Verilog Upload User：jinbokc Size：11K
  • [VHDL] kpjsj.rar Second source to achieve a spread spectrum receiver system, using VHDL language, and have a complete test procedure was
    Category: VHDL-FPGA-Verilog Upload User：nnzqzm Size：348K
  • [VHDL] dds_bate4[1].1.rar In the Quartus software using VHDL language realize DDS, can generate sine, cosine, square, triangle and sawtooth waves.
    Category: VHDL-FPGA-Verilog Upload User：zhibogg Size：1726K
  • [VHDL] notetabs.rar Sine wave VHDL language ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ `
    Category: VHDL-FPGA-Verilog Upload User：baiyoushuo Size：1K