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[
VHDL]
asynch_fifo.rar
FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
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[
VHDL]
an_dcfifo_top_restored.rar
alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
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C/C++]
stock_manage.rar
Inventory management information systems, to achieve the storage, transfer database, query, system management functions
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Java/JSP]
networktools.rar
using java development of the web-based tools, a Web browser, FTP network file transfer, TELNET client examples, etc.
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[
Delphi]
Trans.rar
I write with Delphi-based TCP/IP data transfer procedures for the equivalent of soft routing soft routing flu Interested friends can reference
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