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VHDL]
RISC.rar
RISC (reduced instruction set computer) stored procedures source code of the state machine
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Java/JSP]
KModies.rar
focal point for the preparation of k and debug a program, it will the user to enter the formal conversion to a state diagram and matrix forms express the determination of DFA. 1. The formal type is converted to NFA2. Will determine the NFA into a DFA
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C/C++]
sysinfo_for_e2.rar
moto e2 Overview of real-time system source code, use the qt interface, you can display the current cpu, memory, and data state, the use of arm-linux-gcc compiler, and to build the corresponding qt environment
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WORD]
exampleofdesignsimpl
Chination free e-mail system design system requirements outline design document examples and the corresponding State Note subscript
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Matlab]
InvertedPendulumSystem.zip
... of an inverted pendulum system mathematical model, the application of state feedback control design configuration of the system pole inverted pendulum system controller, to achieve its state-feedback, so that the work of the inverted pendulum system ...
Category:
matlab Upload User：
pbbattery Size：
273K
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VHDL]
design_a_stopwatch_using_VHDL.rar
Designed to be a cis-timing and countdown stopwatch. Required time ranges from 00.0S ~ 99.9S, with three digital tube display, with three light-emitting diode display correctly the following states: the countdown state, cis-time status, standby mode
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Visual C++ (VC++)]
statemachine.rar
Systemc language designed using a state machine, mainly consists of two processes, the simulation results show that the state machine can work properly
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Java/JSP]
rs.rar
Reply by the state was very much opposed to the rich and East is Red
Category:
E-Books Upload User：
zlf790605 Size：
2389K
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Visual C++ (VC++)]
3.rar
Finite state machine, the use of ants looking for food preparation VC6.0 simulation procedures
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