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  • [Java/JSP] missionaris.zip missionaries and cannibal problem solved using java state file
    Category: Java Develop Upload User:weituo13 Size:526K
  • [Java/JSP] 8puzzlesolve.zip This an 8-puzzle solver. You input the current state of your annoying little 8 puzzle and it ll use the Hillclimbing Algorithm to calculate a list of moves which you can use to solve the puzzle. It is written in C++ with an interactive text mode based ...
    Category: Windows Develop Upload User:dinghexing Size:6K
  • [C/C++] sman10-sources.zip ... which manufacturers did not provide or which are difficult or impossible to do manually. SMan helps keep your UIQ device running in a "healthy" state and, to a certain degree, allows you to customize the behavior of your system device.
    Category: Symbian Upload User:qc6341805 Size:27K
  • [Visual C++ (VC++)] deadline.Rar ... introduction of Qinghua University Press published), co-authored with Dimulishite the "state of the art of software" (Software State-of-the-Art), and "why so much software overhead?" (Why Does Software Cost So Much ) ...
    Category: Software Engineering eBooks Upload User:venus61 Size:84K
  • [C/C++] mp3 programming cook book S_CXV.rar mp3 programming cook book in C. README file for yampp-3 source code 2001-05-27 This is the current state of the yampp-3 source code, 2001-05-27. This code is intended to run on Rev. B of the yampp-3 PCB, but can ofcourse be used on compatible systems as ...
    Category: USB develop Upload User:lyinxa Size:49K
  • [Asm] slaa123.rar Solid State Voice Recorder Using Flash MSP430
    Category: Embeded-SCM Develop Upload User:beigen Size:66K
  • [Visual C++ (VC++)] WTLMDIChildMax.zip ... child, then create a new MDI child, the children all go back to their "restored" state. What you d typically expect as a user is that the new child would be in the "maximized" state just like the last active child had been.
    Category: GUI Develop Upload User:shzhengda Size:14K
  • [VHDL] ebook_verilog_fine_state_machine.zip Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and ...
    Category: VHDL-FPGA-Verilog Upload User:bjxdktwx Size:119K
  • [Matlab] TimePre2.rar This is mathematically equivalent to setting the initial state estimate
    Category: Windows Develop Upload User:dgwoman Size:1K
  • [Visual C++ (VC++)] ContentbasedMultimediaInformationalRetrieval.rar ... and search paradigms, user studies, affective computing, learning, semantic queries, new features and media types, high performance indexing, and evaluation techniques. Based on the current state of the art, we discuss the major challenges for the future.
    Category: Other eBooks Upload User:civysales Size:192K