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  • [VHDL] servo_motor_top.rar Synthesis of control for two servo_motor s with state machine for 3 cyclone fpga vhdl language.
    Category: software engineering Upload User:summer Size:1K
  • [Matlab] BlockMatchingAlgoMPEG.zip ... This project contains the project report and source code by Aroh Barjatya for Digital Image Processing Class at Utah State University. Following is a short description of the m files in this zip motionsEstAnalysis.m Script to execute all ...
    Category: matlab Upload User:ly767269 Size:116K
  • [PDF] Power_On_Sequence_State_Machine_Test_Suite.zip Power On Sequence State Machine Test Suite for SATA Hosts and Devices
    Category: Other eBooks Upload User:hongjingdq Size:328K
  • [PDF] solid_state.rar THIS IS EBOOK OF SOLID STATE PHYSICS
    Category: Embeded-SCM Develop Upload User:yrazhzh58 Size:302K
  • [PDF] chap05.rar this is solid state document
    Category: WinSock-NDIS Upload User:tqm1204 Size:1427K
  • [VHDL] CIC_Moore.rar It is a complete project of Cache Interface Controller programmed in VHDL using the logic of Moore State Machine
    Category: VHDL-FPGA-Verilog Upload User:nic7510 Size:353K
  • [Visual C++ (VC++)] 06.rar ... Work or its contents.The Work is sold AS IS and WITHOUT WARRANTY. You may have other legal rights, which vary from state to state. In no event will Makers be liable to you for damages, including any loss of profits, lost savings, or other incidental ...
    Category: C++ eBooks Upload User:buxie88 Size:5804K
  • [Delphi] TjStik.ZIP ... should provide a total solution for anyone that needs to use a Joystick. TFlightJoystick combines a visual joystick state representation with Joystick access and even seamless joystick replacement with a mouse. This means that programs using this ...
    Category: Driver Develop Upload User:wangdeqi99 Size:13K
  • [C/C++] 22048728.rar ... time of one or more of the system variables. Controllers are required to ensure satisfactory transient and steady-state behavior for these engineering systems. To guarantee satisfactory performance in the presence of disturbances and model uncertainty, ...
    Category: SCM Upload User:szdianjin Size:3098K
  • [VHDL] FIR.rar The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. The ...
    Category: VHDL-FPGA-Verilog Upload User:zfsfly Size:1K