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  • [PDF] McGrawHill_VHDL_Programming_by_Example_4th_Ed_upd Electronic and system matlab simulation
    Category: VHDL-FPGA-Verilog Upload User:jianyi Size:1815K
  • [Matlab] csma.rar CSMA model simulation, can refer to slotted CSMA simulation
    Category: source in ebook Upload User:market2 Size:1K
  • [Matlab] AQUILA.zip AQUILA is a MATLAB toolbox for the one- or tw odimensional simulation of the electronic pr% operties of GaAs/AlGaAs semiconductor% nanos tructures.
    Category: matlab Upload User:gtz2001 Size:82K
  • [Others] leon3-altera-ep2s60-ddr.rar ... -on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
    Category: Graph Drawing Upload User:qdrintftf Size:101K
  • [Visual C++ (VC++)] 5.zip A simulation of the famous MineSweeper game by Microsoft.
    Category: Button control Upload User:zshongtai8 Size:47K
  • [C/C++] Dynalith.SoC.Design.and.Verification.Using.System ... is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ (see also discrete event simulation). SystemC makes it possible to simulate concurrent processes, each described using plain C++ syntax. SystemC processes can ...
    Category: Other eBooks Upload User:xin_gongyi Size:14607K
  • [C/C++] Fuzzy-Simulation-1.rar Tsinghua University, teaching in the planning uncertainty simulation algorithm fuzzy one
    Category: AI-NN-PR Upload User:jerryjzp Size:3K
  • [Matlab] rfid_model.rar A system simulation environment in Matlab/Simulink of RFID is constructed in this paper. Special attention is emphasized on ... coding method,parameters of building blocks,and operation distance.Finally,some simulation results are presented in this paper.
    Category: matlab Upload User:xhd1221 Size:2050K
  • [Matlab] BPSK.zip simulation simulink block diagram to realize BPSK modulation
    Category: matlab Upload User:any003 Size:133K
  • [Others] CLOCK_co-design_of_C_and_Verilog.rar A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
    Category: Other systems Upload User:yisteven Size:37K