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  • [Asm] Dancing_Lights.rar program for Night Raider Sequence
    Category: Embeded-SCM Develop Upload User:weixd009 Size:1K
  • [Asm] Night_Rider.rar program for Night Raider Sequence on PIC17C756A
    Category: Other systems Upload User:surewinhk Size:1K
  • [PDF] wcdmathesis.rar ... spread, delay spread, and incorporate additional concepts such as direction of arrival and antenna array geometry. PN sequence properties and generation are studied. Spreading and scrambling techniques are present. RAKE receiver and multiuser detection ...
    Category: Communication Document Upload User:stjcfj Size:549K
  • [Others] mani.rar MMSE Generation of a naive training sequence.. Assuming BPSK modulation
    Category: Communication-Mobile Upload User:nnrqgd Size:2K
  • [VHDL] PRBS.rar pseudo random bit sequence generator
    Category: Modem program Upload User:syj197997 Size:10K
  • [VHDL] gen.rar sequence generator -hardware implementation (structural)
    Category: Other systems Upload User:qqy_2008 Size:2K
  • [Matlab] vdnclaba.rar ... below creates a frequency-flat Rayleigh fading channel object and uses it to process a DBPSK signal consisting of a single vector. Notice that the example uses filter before awgn this is the recommended sequence to use when you combine fading with AWGN
    Category: Other systems Upload User:company Size:1K
  • [Matlab] Code_Find.rar This is a matlab code for m sequence code finding
    Category: matlab Upload User:geshan168 Size:1K
  • [Matlab] MATLAB.rar ... which the user can compress data sets using the codec RLE. The graphical interface supports the following functions: Input data sequence using appropriate control. What effect on the screen. It should appear as separate tables of data value and length ...
    Category: Other eBooks Upload User:digiduo Size:1K
  • [VHDL] STUDENTS_SCORE.zip ... be high when OUTPUT is valid, and test pattern will compare your output signals to the correct answer. 7. The valid output sequence must be continuous without any interruption. 8. Input delay and output delay are 0.5*clock period. 9. After synthesis, ...
    Category: Project Design Upload User:dgluyaocai Size:3275K