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  • [TEXT] DS1340.zip Initializing sequence for DS1340
    Category: Other Embeded program Upload User:dgtxzm Size:1K
  • [Visual C++ (VC++)] probaligngui_beta_1.3.tar.gz A multiple sequence alignment program
    Category: Embeded-SCM Develop Upload User:yanoll Size:1753K
  • [C/C++] tiny-parse.zip ... in bold are terminals): 1. program-> declarations stmt-sequence 2. declarations-> decl declarations |² 3. decl-> ... -> identifi er { , identifi er } 6. stmt-sequence-> statement { statement } 7. statement-> if-stmt | ...
    Category: Windows Develop Upload User:yyled8 Size:1240K
  • [Matlab] FastWalshHadamardTransform.rar ... . This algorithm uses a Cooley-Tukey type signal flow graph and is implemented in N log2 N additions and subtractions. Data sequence length must be an integer power of 2. The inverse transform is the same as the forward transform except for the ...
    Category: Windows Develop Upload User:gyjjlc Size:2K
  • [Asm] presepe5_asm.zip Sequence on of using 8951
    Category: assembly language Upload User:zql_0711 Size:417K
  • [VHDL] Sequence-detector-design.rar Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
    Category: VHDL-FPGA-Verilog Upload User:aikcheong8 Size:30K
  • [Matlab] codeunsymmetrical.rar ... to that of symmetrical faults, except that in the case of unsymmetrical faults, the three-phase power system is represented by its sequence networks i.e zero, positive and negative sequence. Also, the effects of Δ-Y transformers phase shift are considered ...
    Category: Windows Develop Upload User:zouwulin Size:1K
  • [Visual C++ (VC++)] Rtp(rtcp).zip Include payload type identifier Sequence Nubering Time Stamping Delivery monitoring
    Category: IP Phone/VOIP/Live Upload User:bbbvv7 Size:17K
  • [VHDL] digital_lock.rar Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by pressin any key //From any state pressin ...
    Category: VHDL-FPGA-Verilog Upload User:fanny_iso Size:7K
  • [Matlab] 2221901171942007418161516204577.rar this program realize the DEC, 1998 super resolution algorithm. SR image is obtained from LR image sequence.
    Category: Graph Recognize Upload User:rbhqzshs Size:17480K